Latest submicron technologies enable the design of complex Systems On A Chip (SOC), consisting of hundreds of millions transistors on a single piece of silicon. As a result, the SOC design is a complex and time consuming process. Hence various measures are needed for acceleration of the design phase. At each design level intermediate results are compared to their design objectives. In the case of no match to the design objectives, design steps must be iterated, using modified design specifications. These time consuming iterations can be avoided or at least reduced as much as early design steps are directed to the best match of the design objectives.

    The idea of this site is design space exploration at the Conceptual Level prior to the design phase of a circuit, narrowing the design space to the most feasible architectural candidates. Analytical models for the exploration of SOC cost and performance at the Conceptual Level are under development and will be made available at this site step by step.

    Considering the costs of silicon, chip size estimation is of high interest. An accurate chip size estimation needs detailed knowledge of the transistor densities of a semiconductor process. This web site introduces a novel and simplified analytical chip size estimator, which is independent of manufacturer specific process data. CMOS processes are characterized by only three parameters. These are the drawn gate length and the used numbers of metal layers for logic and for memories. A minimum possible chip size (bestcase) is evaluated from the numbers of transistors for logic and for memories, and from the number of pad cells. The chip size estimator has been derived from a comprehensive analysis of realized VLSI chips. It has been investigated and confirmed either for published VLSIs as well as for latest SOC designs.

For more information see:
H. Jeschke, "Chip Size Estimation for SOC Design Space Exploration," IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), July 2006, pp. 56-62.

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© 2006 - Dr.-Ing. Hartwig Jeschke - Institut für Mikroelektronische Systeme - Gottfried Wilhelm Leibniz Universität Hannover